Anil Kali

Distributed arithmetic (DA) is generally used for area-time efficient implementation of inner products, where one of the vectors is fixed and known in advance. Conventional DA architectures cannot be used when both vectors are variable.

This article proposes a novel architecture for computing inner products of variable vectors, where one of the vectors is encoded using the Radix-4 modified booth technique to reduce the logic complexity. The proposed structure for inner-product computation consists of two sections. The first section of the architecture performs a carry-save reduction of the partial inner products of the same weight to two words. During every successive clock cycle, it reduces such partial products of different weights in the order of the lowest to the highest weight. In the second section of the architecture, the pair of reduced words produced by the first section are shift-accumulated. The area, delay, and power saving are achieved by reducing the overall critical path of the structure and the logic complexity in both sections. Cadence Genus synthesizes the proposed architecture. Then, the design is implemented using place-and-route tools like Cadence Innovus for different inner-product lengths and word lengths.