Ehsan is available for hire

Ehsan Moomivand

Verified Expert in Engineering

Digital Systems Architect and Developer

Copenhagen, Denmark

Toptal member since December 4, 2024

Expertise

VHDL Jira Verilog C++Python MATLAB Git FPGA

Bio

Ehsan, a digital systems architect and engineer specializing in FPGA and ASIC platforms, leads multifaceted projects in telecommunication, wireless networks, Ethernet, digital TV broadcasting, and radar/sonar systems. His leadership fosters technical advancements and enforces standardization efforts. As the primary technical lead, Ehsan collaborates with clients and international partners, ensuring the delivery of cutting-edge solutions for FPGA and ASIC based systems.

Portfolio

Prevas

SystemVerilog, Xilinx Vivado, FPGA, RTL

Comcores

VHDL, Verilog, Intel Quartus Prime, ModelSim, CDC, Lint, Git, ASIC, FPGA

Triax A/S

Riviera-PRO, Subversion (SVN), Jira, MATLAB, RTL

Experience

VHDL - 13 years
Xilinx Vivado - 13 years
Jira - 10 years
Subversion (SVN) - 9 years
Lint - 6 years
CDC - 6 years
SystemVerilog - 6 years
VCS - 6 years

Availability

Full-time

Preferred Environment

VHDL, Verilog, SystemVerilog, Xilinx Vivado, Intel Quartus Prime, VCS, CDC, Jira, Lint, FPGA

The most amazing...

...products I've created for FPGA and ASIC platforms include Sat-IP, TDX compact headend, O-RAN radio unit engine, pipelined FFT, and TSN MAC 1G/100G IP cores.

Work Experience

Digital Systems Architect

2024 - 2024

Prevas

Architected the design. Developed digital IP. Implemented and verified a cutting-edge 4G/5G compatible IoT solution on the Xilinx Zynq Ultrascale platform.
Defined requirement specifications that are fully compatible with IEEE standards.
Designed a high-level architecture for a product that met the specified requirements.
Executed gate-level design for a complete Open RAN (O-RAN) compatible 5G IoT control solution incorporating OFDM modulators, PRACH processing, and diverse DSP functionalities.
Supported the digital verification team in finalizing verification to an ASIC grade by achieving comprehensive code and functional coverage.

Technologies: SystemVerilog, Xilinx Vivado, FPGA, RTL

Senior FPGA Engineer

2019 - 2024

Comcores

Developed different IP cores and systems within telecommunication, wireless, and Ethernet groups. Managed responsibilities from design, planning, and implementation to verification across various areas.
Developed IPs such as OFDM modulators/demodulators with FFT/iFFT, O-RAN radio unit engine for LTE, 5G, and PHY processing, MAC IP cores ranging from 1G/2.5G to high-speed 100G with TSN and TSU, digital up/down conversion, and IQ compression.
Built hardware platforms by collaborating with cutting-edge AMD/Xilinx and Intel/Altera FPGA dev boards, conducted system development using Vivado and Quartus for internal IP integration, and performed hardware verification and testing in the lab.
Generated design specs and user manuals for diverse IPs, designed essential components for complete SoC projects, conducted smoke tests to full regression tests, and formulated internal digital libraries.

Technologies: VHDL, Verilog, Intel Quartus Prime, ModelSim, CDC, Lint, Git, ASIC, FPGA

FPGA Engineer

2015 - 2019

Triax A/S

Worked on two main products, TDX and Sat-IP. Developed the new compact headend, blending past legacy features with innovative additions and enhancements.
Programmed in VHDL/Verilog using Lattice Diamond development tools and Xilinx ISE/Vivado design suites.
Tested and verified VHDL/Verilog code using ModelSim and Aldec Riviera-PRO simulation tools.
Configured, tested, and optimized various IP cores, including Ethernet 1G/2.5G, SGMII/Gb/2.5G Ethernet PCS, SERDES PCS, DDR3 memory controller, DDR3 physical interface, FIR filter, PCI-E root complex, and PCI-E endpoint single/multi-function.
Implemented digital video broadcasting (DVB) standards (DSP algorithms) across a wide range, covering DVB-C, DVB-T, and DVB-S and including encoder, decoder, interleaver, and error correction algorithms.
Collaborated with the software team to integrate low-level driver software (C/C++) for hardware and FPGA components within the Linux operating system.
Designed PCB using the OrCAD PCB designer tool to test Maxim RFDAC (MAX5868) with the Xilinx MicroZed evaluation kit.
Collaborated with software and hardware teams to develop project plans, timelines, and milestones for enhancing the TDX modular headend into a new compact headend.
Defined tasks, planned timelines, and generated progress reports utilizing Jira.
Engaged in team coding and managed source code version control through Git and SVN repositories.

Technologies: Riviera-PRO, Subversion (SVN), Jira, MATLAB, RTL

FPGA Engineer

2011 - 2015

APA

Developed different projects regarding radar and sonar systems, object tracking, video surveillance, and monitoring.
Prepared project plan, timeline, and project milestones in cooperation with other teammates for the kickoff meeting with the customer.
Collaborated with technical staff and clients to discuss engineering issues regarding the design and execution of the project.
Prepared technical notes for conceptual engineering and electronic design criteria and reviewed and verified detailed design specifications and technical reports.
Reviewed product specifications and data sheets of Xilinx and Alters’ FPGA, board, kit, and module.
Conducted rapid prototyping of a specific project by using Xilinx development boards and kits.
Reviewed product specifications and data sheets of other electronic equipment such as memories, interfaces, sensors, analog devices, and power circuits.
Oversaw Verilog and VHDL programming, simulating, implementing, and debugging for electronic components and Xilinx/Altera development boards and kits.
Supervised project execution phases, including type and routine tests, site installation, commissioning, startup, and customer handover.

Technologies: VHDL, MATLAB, Xilinx Vivado, ModelSim, RTL

Experience

O-RAN Radio Unit Engine

An O-RAN radio unit engine that includes LTE, 5G, and PHY processing. It uses an OFDM modulator and demodulators, including FFT/IFFT, digital up/down conversion, and IQ compression. It has been tested on Xilinx ultra-scale Virtex FPGA.

SatIp

A local broadcasting system receives satellite signals and converts them to Ethernet protocols. By using precise memory mapping, any delay in video broadcasting is removed, and users can see videos on their phones and laptops without any issues.

TDX Compact Headend

This is a new, versatile, and compact headend that can convert any signal to any signal. It supports DVB-S, DVB-T, DVB-C, HDMI, Ethernet, and other protocols. The system can also communicate with PCI Express.

Skills

Tools

Subversion (SVN), Jira, ModelSim, Git, MATLAB

Languages

VHDL, Verilog, SystemVerilog, C++, Python

Platforms

Riviera-PRO

Other

Xilinx Vivado, Lint, CDC, RTL, VCS, Intel Quartus Prime, FPGA, ASIC

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