Gonzalo Lavigna, Developer in Buenos Aires, Argentina
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Gonzalo Lavigna

Verified Expert  in Engineering

FPGA Engineer and Developer

Buenos Aires, Argentina

Toptal member since December 24, 2024

Expertise
FPGAAlgorithmsVHDLVerilogPythonSystems EngineeringGitLinuxCMATLABNeural Network
Bio

Gonzalo is a senior FPGA engineer with over a decade of experience designing high-performance, reliable FPGA systems for aerospace and defense. His work spans satellite communications, radar systems, and embedded solutions, specializing in VHDL, Verilog, and UVM. Passionate about innovation, Gonzalo has headed multidisciplinary teams and developed FPGA-based DSP and high-speed interfaces for mission-critical projects.

Portfolio

Skyloom Global
Verilog, Verilog HDL, VHDL, Xilinx Vivado, Cocotb, UVM, Questa Sim, GHDL...
Indie Semiconductor
Verilog, Verilog HDL, Git, Subversion (SVN), SystemVerilog, UVM, MATLAB...
INVAP
Altium, OrCAD, FPGA, VHDL, Verilog, UVM, Aerospace & Defense...

Experience

  • Verilog - 12 years
  • Xilinx Vivado - 12 years
  • FPGA - 12 years
  • VHDL - 12 years
  • Questa Sim - 12 years
  • SystemVerilog - 6 years
  • UVM - 6 years
  • Python 3 - 5 years

Availability

Full-time

Preferred Environment

Linux, CODE, VHDL, FPGA, Verilog, SystemVerilog, Questa Sim, RTL, Axis, ASIC

The most amazing...

...thing I've developed is a high-reliability FPGA-based modem for space optical communications, enabling cutting-edge data transmission for satellite systems.

Work Experience

Principal FPGA Engineer

2022 - PRESENT
Skyloom Global
  • Designed and implemented an FPGA-based modem for space optical communications, leveraging Xilinx FPGAs to achieve data rates of up to 25Gbps.
  • Developed error correction protocols, including LDPC, Hamming, and Reed-Solomon, ensuring high reliability for satellite communication systems.
  • Designed and verified an automatic repeat request (ARQ) protocol, improving data integrity and transmission efficiency.
  • Engineered Ethernet interfaces (1G/2.5G/10G/25G) using GMII/RGMII and transceivers, optimizing performance for various communication standards.
  • Implemented AXI4-based datapaths and memory controllers, including DDR handling, to support high-speed data processing.
  • Utilized UVM and cocotb for FPGA verification, reducing testing time and enhancing design robustness.
  • Conducted power and timing analyses to optimize FPGA resource utilization and meet mission-critical timing requirements.
  • Supported client testing activities at dedicated facilities, ensuring seamless integration and validation of the FPGA-based modem under mission-critical conditions, including TVAC and EMI/EMC environments.
  • Developed FPGA systems using Space Development Agency (SDA) standards as a reference, ensuring compliance with modern satellite communication protocols.
Technologies: Verilog, Verilog HDL, VHDL, Xilinx Vivado, Cocotb, UVM, Questa Sim, GHDL, Icarus Verilog, C, DSP, MATLAB, EDAC

Principal ASIC/FPGA Engineer

2021 - 2022
Indie Semiconductor
  • Designed and prototyped critical digital signal processing (DSP) blocks, including FFT modules, for a software-defined MIMO LiDAR system, optimizing signal processing for autonomous vehicle applications.
  • Developed and verified RTL designs for DSP functionality using SystemVerilog and UVM, ensuring high-quality design verification and reducing debugging time.
  • Collaborated with international teams in California and Scotland to integrate FPGA prototypes into system-level architectures, improving cross-functional efficiency.
  • Conducted system-level verification using Cadence tools, such as SimVision and Xcelium, streamlining the simulation process for complex DSP designs.
  • Automated randomization and issue tracking processes using Jira, enhancing project management and issue resolution timelines.
  • Performed FPGA prototyping of an ASIC design, validating critical DSP functionality and enabling early detection of design issues before fabrication.
Technologies: Verilog, Verilog HDL, Git, Subversion (SVN), SystemVerilog, UVM, MATLAB, Verification, Emulation, Validation, FPGA, Xilinx Vivado

Senior Hardware and FPGA Engineer

2012 - 2021
INVAP
  • Developed and verified high-reliability FPGA-based systems for advanced radar and satellite applications, ensuring compliance with strict aerospace and defense standards.
  • Led designing and implementing DSP architectures, optimizing performance for high-speed data acquisition and processing in radar systems.
  • Collaborated cross-functionally with multidisciplinary teams to deliver innovative solutions for space and defense projects, contributing to the success of critical national and international missions.
  • Implemented robust verification methodologies, including the adoption of UVM and simulation-based approaches, enhancing the reliability and efficiency of FPGA designs.
  • Pioneered hardware design optimizations for next-generation satellite payloads, achieving significant improvements in power efficiency and processing throughput.
  • Diagnosed and resolved complex hardware and software anomalies during integration and testing phases, mitigating risks and ensuring mission readiness.
  • Interfaced with stakeholders actively to define and validate subsystem requirements, translating complex mission objectives into reliable, high-performance solutions.
  • Spearheaded end-to-end testing and validation processes, including functional, environmental, and system-level tests, guaranteeing subsystem performance in mission-critical conditions.
Technologies: Altium, OrCAD, FPGA, VHDL, Verilog, UVM, Aerospace & Defense, Systems Engineering, EMI/EMC Compatibility, TVAC, Radiation, Verification, Validation, Hardware, Laboratoy, C, Python 3, Libero IDE, Xilinx Vivado, ModelSim, Questa Sim, Circuit Board Design, Signal Integrety, Radar, CPU Boards, Computer Science, Axis, Wishbone, Reed Solomon, CCSDS, Telecom Equipment & Solutions

Experience

ITBA DSP

https://github.com/gonzalolavigna/itba-dsp
Guided undergraduate and graduate students in designing and implementing FPGA-based projects, focusing on DSP applications. I mentored students in applying industry-standard practices for FPGA development, including module-based design, hardware debugging, and resource optimization. Also, I promoted continuous learning by introducing modern tools and techniques in FPGA development, ensuring students gained skills aligned with current industry demands.

Education

2006 - 2011

Bachelor's Degree in Electrical Engineering

Technological Institute of Buenos Aires - Buenos Aires, Argentina

Skills

Libraries/APIs

Axis, Altium

Tools

MATLAB, Git, Subversion (SVN), Libero IDE, ModelSim, Radar, OrCAD

Languages

VHDL, Verilog, Python 3, Verilog HDL, SystemVerilog, C

Frameworks

CODE

Platforms

Linux

Paradigms

Analog Circuits

Other

FPGA, Xilinx Vivado, Questa Sim, Telecom Equipment & Solutions, DSP, Microcontrollers, Computer Science, Algorithms, Digital Electronics, Validation, Aerospace & Defense, TVAC, Hardware, Wishbone, CCSDS, UVM, Electronics, PCB, Digital Communication, Networks, Controls, Microprocessors, Cocotb, EDAC, Verification, Systems Engineering, Laboratoy, Circuit Board Design, CPU Boards, Reed Solomon, Neural Networks, Antenna Design, Power Electronics, Data Structures, Sensors & Actuators, GHDL, Icarus Verilog, Emulation, EMI/EMC Compatibility, Radiation, Signal Integrety, RTL, ASIC

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