- Digital Design and Verification Engineer2012 - PRESENTElsys Eastern Europe
Technologies: VHDL, TCL, Java, C++, Python, SPECMAN e
- Conducted IP module level verification using SPECMAN, eRM methodology, and e-language.
- Did FPGA-directed SoC verification using a generic test-bench approach and VHDL language.
- Conducted physical verification of FPGA and PCB board design.
- Familiarized myself with DO-254 and SIL-4 security standards.
- Did ASIC/FPGA digital design.
- Junior Software Developer2011 - 2011WIPL-D
- Re-implemented a parser for a custom data description language used in WIPL-D microwave antenna simulation software, improving its performance by 40 times.