VHDL Developer in Belgrade, Serbia

(February 2015) Part of the team which performed IP Module Level verification of the CoreIP module, using SPECMAN e-language and eRM methodology.

(October 2014 – February 2015) Part of the team which performed IP Module Level verification of the ADC module(digital part), using SPECMAN e-language and eRM methodology.

(July 2014 – October 2014) Part of the team which performed IP Module Level verification of the RAM Controller module, using SPECMAN e-language and eRM methodology.

(March 2014 – Jun 2014) Part of the team which performed RTL & Gate-level verification of FPGA design, targeting two Xilinx's Spartan 6, in a railway transport application implementing SIL 4 standard.

(August 2013 - January 2014) Part of the team which performed physical verification of two FPGA designs and two PCB boards, targeting Microsemi ProAsic3 Military FPGA, implementing DO 254 - C standard.

(May 2013 - July 2013) Developed a Java GUI application for maintenance, changing, and initialization of registers for verification purposes.

(July 2012 - February 2013) Part of the team which developed design targeting VIRTEX 6 FPGA in an avionics application, implementing DO 254 standard.

(April 2012 - June 2012) Implementation of “Video to OCP” module with clock synchronization.

(May 2011 - August 2011) Part of the team which developed a microwave graphic simulator. Created a DLL for the core of the symbolic interpreter in the WIPL-D program system and adapted the programming environment for checking, testing, and measuring the DLL's performance.