Harsha H S
Harsha has nearly two decades of experience in software design, architecture, development, and testing across a broad spectrum, from low-level silicon validation, board bring-ups, and device drivers to scalable distributed databases, route planning for autonomous vehicles, and AI applications. He has worked at startups alongside co-founders to bring ideas to life and at MNCs with geographically distributed cross-functional teams. Harsha believes in "simplicity well-tested and -documented."
ExperienceLinux - 20 yearsAlgorithms - 16 yearsC - 15 yearsLinux Kernel - 12 yearsPython - 10 yearsC++ - 10 yearsAgile Software Development - 8 yearsDistributed Systems - 5 years
Linux, C++, C, Python, Distributed Systems, Hypervisors, Algorithms, PyTorch, Cryptography, Assembly
The most amazing...
...thing I've developed is a distributed and hybrid routing service for a fleet of autonomous robotaxis under various weather, traffic, and road constraints.
Order In Chaos Technology LLP
- Implemented a customized key exchange protocol on Gemalto's hardware security module (HSM) using elliptic-curve cryptography.
- Contributed to carving our required compute and memory resources for the workload on a distributed PaaS for AI/machine learning applications, specifically on middleware, similar to how Mesos abstracts all the compute, storage, and memory resources.
- Integrated a transport layer security on top of an HTTP server, written using proprietary eventing and the asyncio framework.
Senior Kernel/Hypervisor and Robotics Engineer
- Developed a proof of concept for an NX network card emulation in QEMU to remove hardware dependency for the Xen on Nitro program.
- Supervised a small team to deliver the same to include TCP checksum and segmentation offloading.
- Maintained the health of accelerated compute infrastructure on Amazon EC2.
- Managed cross-functional stakeholders in hardware, kernel, hypervisor, and GPU compute teams.
- Contributed to the overall quality improvement and upgrade of Xen fleets and, eventually, the migration of the Xen fleet to Xen on Nitro architecture.
- Collected and stored metrics to understand robot behavior and improve operational robustness of scout robots middleware, using the robot operating system to extend battery life.
Senior Software Engineer
- Delivered products as a core founding team member, aimed at explainable AI for convolution neural networks using signal estimation, uncertainty modeling, and concept extraction, and using Cython to package into SDK and integrated keygen licensing.
- Designed an active learning process using uncertainty modeling to feed right and limited data sets to a deep neural network to reduce training time without compromising accuracy.
- Developed and delivered a back-end service using tornado, MySQL, and layer-wise relevance propagation algorithm to explain manufacturing failures, trained using long short-term memory (LSTM) recurrent neural network architecture.
Senior Software/Research Engineer
- Designed, developed, and tested a fleet management system for thousands of autonomous taxis plying on Singapore's city-scale using dynamic shortest path algorithms to route the taxis under various constraints.
- Researched and created constrained assignment algorithms to reduce customer wait time and maximize robotaxi utilization, exploring topics such as ride-sharing and a hybrid mode of transport.
- Developed a grid matching algorithm and worked on GeoJSON data to match customers to available robotaxis in constant time.
- Scaled the service by working on hybrid mode of motion planning using coarse graphs to reduce graph complexity.
Senior Software Engineer
- Reduced network traffic overhead and indexing throughput with a solution designed and developed to optimize MapReduce indexes when document fields are unused.
- Simplified required efforts for the horizontal scaling of eventing nodes by architecting and mentoring on developing and implementing its consensus-free sharding mechanism.
- Applied various improvements and bug fixes in B+ tree implementation and MapReduce indexing using async networking primitives in Erlang.
Senior ASIC Engineer
- Developed microcode for ARMv8 instruction set architecture (ISA) to gain out-of-order benefits with a custom in-order VLIW engine, fusing operations and optimizing hot code block using branch prediction performance metrics.
- Created and maintained the code coverage infrastructure for a management translation software on the microcode engine and a software interpreter handling hypervisor exceptions and slow interrupt paths.
- Improved the random instruction generator to uncover and fix bugs in the simulator and register-transfer level for ARMv8 ISA.
Graphics Software Engineer
- Contributed to the board bring-up process of Ivy Bridge and a next-gen Intel processor as part of the Legacy Video BIOS team, catering to display interfaces such as HDMI, DisplayPort, VGA, and LCD.
- Managed a small team of system admins, video basic input/output system (BIOS) experts, and testing officers to deliver an extended desktop feature in video BIOS for Acer's Iconia line of laptops, which had a dual display in place of a keyboard.
- Collaborated with the system administration team to move our codebase from Rational ClearCase to Git and evangelized embracing Agile practices within the system and video BIOS teams.
Tandberg (Acquired by Cisco)
- Developed a test framework for qualifying a hardware board that supports a 720-pixel camera over USB and worked towards obtaining hardware certifications.
- Created and implemented firmware upgrade mechanisms over USB and universal asynchronous receiver-transmitter interfaces.
- Designed and developed direct memory access drivers for a pulse-width modulation module to deliver the sinusoidal wave over the trapezoidal wave to the bipolar stepper motor used for autofocus and exposure, combatting motor noise.
Design Engineer 2
Montalvo Computer Systems India Pvt. Ltd.
- Implemented microcode for an in-order VLIW machine to mimic an x86_64 architecture's hardware task switching mechanism by saving and restoring register files, the system management mode, and various interrupt paths based on control register entries.
- Added diagnostics for various FP, SSE, and MMX instructions crossing with control register sensitivities and x86 modes, implementing identical behavior in microcode.
- Contributed to enhancing various simulator features.
RMI Corporation (Formerly Raza Microelectronics, Inc.)
- Developed a flash mode for an XLR MIPS simulator to simulate the boot process from flash.
- Collaborated with the team to develop a comprehensive benchmark and stress test suite for testing XLR processors.
- Created a GDB stub and core dump utility in the bootloader to debug crashes of multithreaded applications.
- Ported OpenSSL to bypass the software cryptographic algorithms and use hardware accelerators.
- Complied with Federal Information Processing Standards (FIPS) for the HSM that was part of the XLR system on a chip.
Routing and Assignment Microservices for Robotaxis
The project involved graph pruning for scalability and developing a parallel dynamic shortest path graph algorithm for the coarse-grained routing of taxis from source to destination. A fine-grained map was also downloaded onto the taxi on-demand, enabling the robotaxi to perform motion planning, obstruction avoidance, and lane switching to achieve the final goal, which was to provide customers with an optimal assignment service under various constraints.
I was involved with:
• Conducting a research survey to understand various state-of-the-art shortest path algorithms, decide upon the Ramalingam-Reps algorithm, and implement the back end in C++.
• Developing a simple HTTP server in C++ to receive various goal positions, traffic conditions, and other constraints to be applied to the road network graph.
• Creating an extract, transform, and load (ETL) pipeline to scrape GeoJSON data from OpenStreetMap APIs and remove the fine-grained Uni node to get a scalable graph for the cities the robotaxis operated.
• Implementing assignment microservices using operation research techniques to perform constrained optimization.
Distributed Eventing Framework for Couchbase Events
The eventing framework was a post-trigger mechanism to hook in user-specified functions or operations on every database event. It also provided users to connect functionalities for non-database events such as timers.
I was primarily involved with architecting a consensus-free sharding mechanism for eventing nodes to claim ownership of a set of shards by each node without involving leader election, simplifying the design to a large extent.
I was also involved with various integrations, including:
• The eventing functionality with the Couchbase multi-dimension scaling paradigm, scaling each service independently depending on its workload.
Hardware Security Modules and Cryptography for RMI
I worked towards getting an FIPS certification for HSMs. I also developed OpenSSL and OpenSSH integrations and drivers and implemented an elliptic-curve key exchange algorithm for the Gemalto HSM.
OpenSSL, MPI, Protobuf, REST APIs, PyTorch, Open MPI, NumPy, SciPy, Pandas, Keras, SQLAlchemy, Asyncio, TensorFlow, Node.js
CMake, OpenSSH, GDB, GitLab, GitHub, Jira, Git, GIS, NGINX, Valgrind, Amazon SageMaker, Mesos, Conan, AWS IAM
ETL, Agile Software Development, Object-oriented Programming (OOP), Data Science, DevOps, Functional Programming
Linux, Amazon Web Services (AWS), Docker, NVIDIA CUDA, Xen, Quick EMUlator (QEMU), Amazon EC2, AWS IoT, AWS Lambda
Distributed Systems, Hypervisors, Algorithms, Linux Kernel, Open Source, HSM, ARM, BIOS, Firmware, Bootloaders, Multithreading, Multiprocessing, Deep Neural Networks, Machine Learning, Linux Servers, Cloud, Architecture, Leadership, Embedded Systems, Data Extraction, Team Leadership, APIs, Linux Server Administration, Mathematics, Scripting, Command-line Interface (CLI), Data Engineering, linters, High Code Quality, Cryptography, Complexity Theory, Operations Research, GPU Computing, Cython, Google V8, Graphics Processing Unit (GPU), Boost.Asio, Internet of Things (IoT), Compilers, Hardware Drivers, Device Drivers, Elliptic Curve Cryptography, Neural Networks, Computer Vision, Networking, Asynchronous I/O, Cloud Storage, Virtualization Technology, Virtualization, Cloud Architecture, Serverless, CI/CD Pipelines, AWS Cloud Architecture, Transport Layer Security (TLS), Robot Operating System (ROS), Storage, USB, Groovy Scripting, Firmware over the Air (FOTA), Statistics
JSON, Databases, Amazon S3 (AWS S3), PostgreSQL, Oracle PL/SQL, MySQL, SQLite, Kdb+, Neo4j, Redis
Bachelor's Degree in Computer Science and Engineering
Bapuji Institute of Engineering and Technology - Davanagere, Karnataka, India