Contractor (FPGA/ASIC Design)2017 - 2020Collins Aerospace
Technologies: Python, SystemVerilog, VHDL
- Designed, developed, and verified FPGA components and systems using VHDL and SystemVerilog for radio systems.
- Collaborated with hardware and software development teams.
- Tracked and fixed bugs using Jira as a reporting tool.
- Developed Python scripts to accelerate the hardware calibration process.
Senior System Engineer2015 - 2016Raytheon
Technologies: Python, VHDL
- Migrated various Xilinx ISE projects to Xilinx Vivado.
- Developed and performed system integration and testing using ChipScope, oscilloscope, and Python scripting for automation.
- Collaborated with the software team to investigate and fix errors during hardware integration.
- Designed FPGA architectures, algorithms, code, simulations, and synthesis with device constraints for Xilinx Virtex family FPGAs on custom hardware.
Software Engineer2008 - 2014Schweitzer Engineering Laboratories
Technologies: MATLAB, Perl, VHDL, C++, C
- Developed firmware for transmission line protective relays with a ColdFire processor in C/C++ and VHDL for Xilinx Spartan3/Spartan3a FPGA on custom hardware.
- Designed test equipment in C/C++ and VHDL for debugging electronics.
- Tracked and fixed bugs using ClearQuest as a reporting tool.
- Updated a time and date management system to understand UTC and daylight savings.
- Integrated SNTP and PTP protocols into the date and time management system.
- Participate on a change control board to discuss software and firmware change requests for product features, customer needs, and vendor issues.
- Improved the firmware boot program to accept compressed files to reduce the update time.