
Navoda Perera
Verified Expert in Engineering
FPGA Developer
Chantilly, VA, United States
Toptal member since September 30, 2019
Navoda has more than three years of experience in digital system design using VHDL/Verilog for FPGAs (Xilinx/Altera). He is equally proficient with C/C++ and Python. Navoda has a bachelor's degree in electronics and currently writing the thesis for his master's degree in embedded systems at the University of Twente in the Netherlands. Navoda has worked remotely with a number of companies in Sri Lanka, Netherland, Switzerland, and the USA.
Portfolio
Experience
- VHDL - 4 years
- Git - 4 years
- Linux - 4 years
- FPGA - 4 years
- C++ - 4 years
- Verilog - 4 years
- Xilinx Vivado - 4 years
- Python - 3 years
Availability
Preferred Environment
Git, Linux, Visual Studio Code (VS Code)
The most amazing...
...project I've worked on was developing an FPGA core to acquire high speed raw data from a radar sensor through an LVDS interface.
Work Experience
Thesis Student
ASML, Veldhoven, Netherlands
- Worked on offloading numerical calculations to hardware accelerators (C/C++).
- Contributed to modeling performance of specific routines on CPU/GPU.
- Investigated hardware acceleration efforts of numerical libraries in literature.
Intern
ABB Corporate Research Center, Baden, Switzerland
- Developed an FPGA IP for high speed LVDS data acquisition (VHDL/ Xilinx Vivado).
- Configured a Linux OS to run on an embedded platform (Xilinx Zynq MPSoC).
- Worked on signal processing software (Python) on a Xilinx MPSoC (PS) to process data that is being streamed from the FPGA (PL).
- Configured the firmware of a TI radar sensor for specific application (C++).
- Made use of Xilinx high speed transceivers for high speed serial communication.
Firmware Engineer
3T, Enschede, Netherlands
- Developed a Python-based program to generate documentation and source files for hardware register maps.
- Updated a 1-wire EEPROM controller for the FPGA (VHDL/Modelsim).
- Used Modelsim for extensive testing.
Consulting Application Engineer (Remote)
Wave Computing, Campbell, USA (Independent Contractor)
- Developed C++ applications targeted for the CGRA.
- Debugged custom compilers and assembly level programs.
- Developed applications for a CGRA using dataflow models.
Consulting Application Engineer (Remote)
Wave Computing, Campbell, USA (Through ParaQum Technologies)
- Developed applications for a CGRA using dataflow models.
- Created a machine code instruction verifier using Python.
- Debugged custom compilers and assembly level programs.
- Gained exposure to state of the art processor architecture and parallel computing techniques.
Electronic Engineer
ParaQum Technologies, Colombo, Sri Lanka
- Developed a 10 Gbps network packet header classification module on FPGA (Verilog).
- Researched on data de-duplication/compression on FPGA for network optimization (C++/ Verilog).
- Verified a hardware-based AES IP Core using test benches (Modelsim/SystemVerilog).
Intern
ParaQum Technologies, Colombo, Sri Lanka
- Developed a hash-based frame verification module for an HEVC Decoder on FPGA (Verilog/Xilinx Vivado/Modelsim).
- Configured the RIFFA Framework for FPGA and PC Communication using PCI Express Gen 2.
- Performed some software automation tasks for hardware verification (Python).
Experience
FPGA Core for Raw Radar Data Acquisition
Python-based Register Map Automation
A Python-based tool was developed to read the data from an Excel sheet and automatically generated required files based on templates.
Users were able to define their own Word templates and source/text file templates which will be used to populate with register map data.
Machine Code Instruction Verifier Using Python
Multi-threaded Real-time Application on a 32-core Processor System
Several throughput bottlenecks were successfully addressed for a final performance of the game at 60 fps at a resolution of 640x480. A FIFO ring supported by the hardware was used for synchronization between tasks.
This project was done as part of the Real-time Systems 2 course at the University of Twente.
Vision-in-the-loop Application Using Software and Hardware Systems
This project was done as part of the Embedded Systems Laboratory course at the University of Twente.
32-bit MIPS Processor Using VHDL
Data De-duplication for Network Optimization on FPGA
10 Gbps Network Packet Header Classification on FPGA
FPGA-based Network Security Engine
Education
Master's Degree in Embedded Systems
University of Twente - Enschede, Netherlands
Bachelor's Degree in Electronic and Telecommunication Engineering
University of Moratuwa - Colombo, Sri Lanka
Certifications
IELTS
IELTS
Diploma in Management Accounting
Chartered Institute of Management Accountants (CIMA)
Skills
Libraries/APIs
Jenkins Pipeline, PyTorch, Keras
Tools
Git, GitLab, Sublime Text 3, Xilinx Ise, ModelSim, MATLAB, Atom, Jira, Jenkins, Altera Quartus
Languages
Python, VHDL, C, C++, SystemVerilog, Verilog
Platforms
Linux, Windows, Visual Studio Code (VS Code), NVIDIA CUDA
Paradigms
Agile Software Development, Functional Programming
Other
FPGA, Xilinx Vivado, Web Scraping, Languages, Graphics Processing Unit (GPU), Machine Learning, Encryption, Network Analysis, Algorithms
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