Sangam J K, Developer in Pune, Maharashtra, India
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Sangam J K

Verified Expert  in Engineering

FPGA Engineer and Developer

Pune, Maharashtra, India

Toptal member since December 13, 2024

Expertise
VHDLCMATLAB
Bio

Sangam is a skilled FPGA register-transfer level (RTL) design engineer with a strong background in developing high-performance digital systems. With expertise in HDL languages like Verilog and VHDL, he excels in crafting optimized, reliable, and scalable designs tailored to meet specific requirements. Known for precision and innovation, Sangam delivers solutions that drive efficiency and success in diverse industries.

Portfolio

Bit Mapper Integration Technologies Pvt
Verilog HDL, VHDL, C, MATLAB
iWave Systems Technologies Pvt
Verilog HDL, VHDL, C, MATLAB

Experience

  • Windows 10 - 6 years
  • Vitis SDK - 5 years
  • Xilinx Vivado - 5 years
  • Intel Quartus Prime - 5 years
  • Verilog HDL - 5 years
  • VHDL - 5 years
  • MATLAB - 4 years
  • Windows 11 - 2 years

Availability

Part-time

Preferred Environment

Windows 10, Xilinx Vivado, Vitis SDK, Zynq-7000, Virtex UltraScale+ FPGAs, Windows 11, MATLAB, Intel Quartus Prime

The most amazing...

...project I've worked on involves completing the Intel Agilex FPGA-based system-on-modules (SoMs) board bring-up from scratch.

Work Experience

Technical Lead

2023 - PRESENT
Bit Mapper Integration Technologies Pvt
  • Headed the implementation of FPGA prototypes for complex systems, enabling early hardware validation and reducing debugging time.
  • Mentored junior engineers on best practices in FPGA design and verification, fostering a skilled and productive team environment.
  • Managed technical risks by conducting detailed design reviews and fault analysis, achieving a 98% success rate in first-time implementations.
Technologies: Verilog HDL, VHDL, C, MATLAB

Senior FPGA Design Engineer

2019 - 2023
iWave Systems Technologies Pvt
  • Integrated multiple IP cores into FPGA designs, enabling seamless interoperability and reducing development time by 20%.
  • Collaborated with cross-functional teams to translate system-level requirements into efficient FPGA architectures, ensuring project goals were met within deadlines.
  • Conducted in-depth post-implementation validation on hardware, ensuring compatibility and robustness under varying operational conditions.
Technologies: Verilog HDL, VHDL, C, MATLAB

Experience

ADC Data-capturing Board

Executed high-performance data processing and computation using Virtex UltraScale+ FPGA. I ensured reliable high-speed data transfer using the Aurora protocol. It also includes efficient data storage in DDR memory on Zynq-7,000 FPGA and seamless Ethernet transmission for real-time GUI plotting and analysis.

Skills

Tools

MATLAB

Languages

Verilog HDL, VHDL, C

Other

Intel Quartus Prime, Xilinx Vivado, Windows 11, Windows 10, Vitis SDK, Zynq-7000, Virtex UltraScale+ FPGAs, Universal Asynchronous Receiver/Transmitter (UART)

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