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Navoda Perera
Verified Expert in Engineering
FPGA Developer
Chantilly, VA, United States
Toptal member since September 30, 2019
Bio
Navoda has more than three years of experience in digital system design using VHDL/Verilog for FPGAs (Xilinx/Altera). He is equally proficient with C/C++ and Python. Navoda has a bachelor's degree in electronics and currently writing the thesis for his master's degree in embedded systems at the University of Twente in the Netherlands. Navoda has worked remotely with a number of companies in Sri Lanka, Netherland, Switzerland, and the USA.
Portfolio
ASML, Veldhoven, Netherlands
NVIDIA CUDA, Graphics Processing Unit (GPU), Git, Linux, C++, C
ABB Corporate Research Center, Baden, Switzerland
ModelSim, Xilinx Vivado, Git, VHDL, FPGA, Linux, Python
3T, Enschede, Netherlands
Git, ModelSim, VHDL, FPGA, Python
Experience
- VHDL - 4 years
- Git - 4 years
- Linux - 4 years
- FPGA - 4 years
- C++ - 4 years
- Verilog - 4 years
- Xilinx Vivado - 4 years
- Python - 3 years
Work Experience
Thesis Student
2019 - 2020
ASML, Veldhoven, Netherlands
- Worked on offloading numerical calculations to hardware accelerators (C/C++).
- Contributed to modeling performance of specific routines on CPU/GPU.
- Investigated hardware acceleration efforts of numerical libraries in literature.
Technologies: NVIDIA CUDA, Graphics Processing Unit (GPU), Git, Linux, C++, C
Intern
2019 - 2019
ABB Corporate Research Center, Baden, Switzerland
- Developed an FPGA IP for high speed LVDS data acquisition (VHDL/ Xilinx Vivado).
- Configured a Linux OS to run on an embedded platform (Xilinx Zynq MPSoC).
- Worked on signal processing software (Python) on a Xilinx MPSoC (PS) to process data that is being streamed from the FPGA (PL).
- Configured the firmware of a TI radar sensor for specific application (C++).
- Made use of Xilinx high speed transceivers for high speed serial communication.
Technologies: ModelSim, Xilinx Vivado, Git, VHDL, FPGA, Linux, Python
Firmware Engineer
2018 - 2019
3T, Enschede, Netherlands
- Developed a Python-based program to generate documentation and source files for hardware register maps.
- Updated a 1-wire EEPROM controller for the FPGA (VHDL/Modelsim).
- Used Modelsim for extensive testing.
Technologies: Git, ModelSim, VHDL, FPGA, Python
Consulting Application Engineer (Remote)
2018 - 2019
Wave Computing, Campbell, USA (Independent Contractor)
- Developed C++ applications targeted for the CGRA.
- Debugged custom compilers and assembly level programs.
- Developed applications for a CGRA using dataflow models.
Technologies: Linux, Jenkins, Git, Languages, Python, C++
Consulting Application Engineer (Remote)
2016 - 2018
Wave Computing, Campbell, USA (Through ParaQum Technologies)
- Developed applications for a CGRA using dataflow models.
- Created a machine code instruction verifier using Python.
- Debugged custom compilers and assembly level programs.
- Gained exposure to state of the art processor architecture and parallel computing techniques.
Technologies: Linux, Jenkins, Git, Languages, Python, C++
Electronic Engineer
2016 - 2018
ParaQum Technologies, Colombo, Sri Lanka
- Developed a 10 Gbps network packet header classification module on FPGA (Verilog).
- Researched on data de-duplication/compression on FPGA for network optimization (C++/ Verilog).
- Verified a hardware-based AES IP Core using test benches (Modelsim/SystemVerilog).
Technologies: Python, Git, Linux, C++, SystemVerilog, Verilog, FPGA
Intern
2014 - 2015
ParaQum Technologies, Colombo, Sri Lanka
- Developed a hash-based frame verification module for an HEVC Decoder on FPGA (Verilog/Xilinx Vivado/Modelsim).
- Configured the RIFFA Framework for FPGA and PC Communication using PCI Express Gen 2.
- Performed some software automation tasks for hardware verification (Python).
Technologies: Python, Git, Linux, C++, SystemVerilog, Verilog, FPGA
Project History
FPGA Core for Raw Radar Data Acquisition
The system was developed for a Xilinx Zynq Ultrascale MPSoC. An IP on the FPGA received raw data through an LVDS interface from a TI radar sensor. The data is forwarded to the memory through DMA, which is read by the signal processing software running on Linux in one of the processors.
Python-based Register Map Automation
When defining register maps for hardware systems, a lot of information is duplicated in several types of files.
A Python-based tool was developed to read the data from an Excel sheet and automatically generated required files based on templates.
Users were able to define their own Word templates and source/text file templates which will be used to populate with register map data.
A Python-based tool was developed to read the data from an Excel sheet and automatically generated required files based on templates.
Users were able to define their own Word templates and source/text file templates which will be used to populate with register map data.
Machine Code Instruction Verifier Using Python
A Python-based program to verify a tool-generated machine code against an assembly instruction schedule.
Multi-threaded Real-time Application on a 32-core Processor System
An arcade game called "Bubble Trouble" was implemented on a 32-core processor real-time system that was deployed on a Virtex 7 FPGA.
Several throughput bottlenecks were successfully addressed for a final performance of the game at 60 fps at a resolution of 640x480. A FIFO ring supported by the hardware was used for synchronization between tasks.
This project was done as part of the Real-time Systems 2 course at the University of Twente.
Several throughput bottlenecks were successfully addressed for a final performance of the game at 60 fps at a resolution of 640x480. A FIFO ring supported by the hardware was used for synchronization between tasks.
This project was done as part of the Real-time Systems 2 course at the University of Twente.
Vision-in-the-loop Application Using Software and Hardware Systems
A given setup with a camera fixed to a pan-tilt motor combination was programmed to implement a vision-in-the-loop application. In the final implementation, the camera followed an identified object in its field-of-view in real-time. A combination of FPGA based IPs and real-time software was used for control.
This project was done as part of the Embedded Systems Laboratory course at the University of Twente.
This project was done as part of the Embedded Systems Laboratory course at the University of Twente.
32-bit MIPS Processor Using VHDL
A processor for a subset of the MIPS 32 bit ISA was developed by a group of 4 students for the Design of Digital Systems module at the University of Twente. The processor description was done using VHDL and simulated for custom assembly programs.
Data De-duplication for Network Optimization on FPGA
Research was done for efficient data de-duplication techniques for network packets. A software (C) model was developed to reflect hardware implementation.
10 Gbps Network Packet Header Classification on FPGA
A Cuckoo Hash-based network packet classification module capable of handling network rates up to 10 Gbps.
FPGA-based Network Security Engine
A hardware-based network intrusion detection system (NIDS) that is capable of processing packets at a rate of 1 Gbps. The system utilizes the open-source rule base provided by Snort. The NIDS was implemented on a Xilinx VC707 development board, which consists of a Virtex-7 series FPGA.
Education
2018 - 2020
Master's Degree in Embedded Systems
University of Twente - Enschede, Netherlands
2011 - 2016
Bachelor's Degree in Electronic and Telecommunication Engineering
University of Moratuwa - Colombo, Sri Lanka
Certifications
APRIL 2018 - APRIL 2020
IELTS
IELTS
JUNE 2013 - PRESENT
Diploma in Management Accounting
Chartered Institute of Management Accountants (CIMA)
Skills
Libraries/APIs
Jenkins Pipeline, PyTorch, Keras
Tools
Git, GitLab, Sublime Text 3, Xilinx Ise, ModelSim, MATLAB, Atom, Jira, Jenkins, Altera Quartus
Languages
Python, VHDL, C, C++, SystemVerilog, Verilog
Platforms
Linux, Windows, Visual Studio Code (VS Code), NVIDIA CUDA
Paradigms
Agile Software Development, Functional Programming
Other
FPGA, Xilinx Vivado, Web Scraping, Languages, Graphics Processing Unit (GPU), Machine Learning, Encryption, Network Analysis, Algorithms
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