Goran Ognjanovic, Developer in Belgrade, Serbia
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Goran Ognjanovic

Verified Expert  in Engineering

Verification Developer

Belgrade, Serbia

Toptal member since March 31, 2015

Expertise
GitCC++VHDLSystemVerilog
Bio

Goran has more than nine years of experience working as a design verification engineer. Equally capable of leading teams and delivering directly, he is versed in IP module-level verification, Specman, and SystemVerilog/UVM. He has worked on Convolutional Neural Networks accelerator IP verification and RISC-V full-chip verification and loves to keep up with the current trends. His engineering mindset and step-by-step approach, while respecting strict deadlines, distinguishes his work.

Availability

Part-time

Preferred Environment

SystemVerilog, Specman, UVM, Verification, ASIC, SimVision Debug, Object-oriented Programming (OOP), Aspect-oriented Programming

The most amazing...

...thing was acting as a verification technical team leader on CNN Convolutional Neural Networks accelerator IP project.

Work Experience

Digital Design and Verification Engineer

2012 - PRESENT
Elsys Eastern Europe
  • Conducted IP module level verification using SPECMAN, eRM methodology, and e-language.
  • Did FPGA-directed SoC verification using a generic test-bench approach and VHDL language.
  • Conducted physical verification of FPGA and PCB board design.
  • Familiarized myself with DO-254 and SIL-4 security standards.
  • Did ASIC/FPGA digital design.
Technologies: Specman, C++, VHDL

Junior Software Developer

2011 - 2011
WIPL-D
  • Re-implemented a parser for a custom data description language used in WIPL-D microwave antenna simulation software, improving its performance by 40 times.
Technologies: C++, C

IP Module Verification for Texas Instruments Germany

(February 2015) Part of the team which performed IP Module Level verification of the CoreIP module, using SPECMAN e-language and eRM methodology.

IP Module Verification for Texas Instruments Germany

(October 2014 – February 2015) Part of the team which performed IP Module Level verification of the ADC module(digital part), using SPECMAN e-language and eRM methodology.

IP Module Verification for Texas Instruments Germany

(July 2014 – October 2014) Part of the team which performed IP Module Level verification of the RAM Controller module, using SPECMAN e-language and eRM methodology.

RTL & Gate-level Verification for ALSTOM Transport

(March 2014 – Jun 2014) Part of the team which performed RTL & Gate-level verification of FPGA design, targeting two Xilinx's Spartan 6, in a railway transport application implementing SIL 4 standard.

Physical Verification for SAFRAN Aerospace

(August 2013 - January 2014) Part of the team which performed physical verification of two FPGA designs and two PCB boards, targeting Microsemi ProAsic3 Military FPGA, implementing DO 254 - C standard.

Java Application for ELSYS Eastern Europe Internal Development

(May 2013 - July 2013) Developed a Java GUI application for maintenance, changing, and initialization of registers for verification purposes.

FPGA Verification for THALES Avionics

(July 2012 - February 2013) Part of the team which developed design targeting VIRTEX 6 FPGA in an avionics application, implementing DO 254 standard.

ASIC Digital Design for ELSYS Eastern Europe Internal Development

(April 2012 - June 2012) Implementation of “Video to OCP” module with clock synchronization.

C++ Programing for Wipl-D

(May 2011 - August 2011) Part of the team which developed a microwave graphic simulator. Created a DLL for the core of the symbolic interpreter in the WIPL-D program system and adapted the programming environment for checking, testing, and measuring the DLL's performance.
2011 - 2014

Master's Degree in Computer Science

University of Belgrade - Belgrade, Serbia

2006 - 2011

Bachelor's Degree in Computer Science

University of Belgrade - Belgrade, Serbia

Tools

Specman, Xcelium, ModelSim, Git

Languages

SystemVerilog, C, C++, VHDL

Paradigms

Object-oriented Programming (OOP), Aspect-oriented Programming

Other

UVM, SimVision Debug, Verification, Design

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