Bharath Reddy, Developer in Hyderabad, Telangana, India
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Bharath Reddy

Verified Expert  in Engineering

Design Engineer and Developer

Hyderabad, Telangana, India
Toptal Member Since
December 1, 2023

Bharath is a design engineer passionate about hardware architecture, RTL design, edge computing, artificial intelligence, and AI chipsets. With nine years of experience in the IT sector, he has successfully built projects from the ground up and led them to completion. Bharath's expertise in the latest technologies, coupled with his strong leadership skills, enables him to drive impactful projects and deliver tangible results for businesses.


Imagination Technologies
RTL, Verilog, AIX, Architecture, PCIE, CXL, MacOS, STA, Lint, CDC, Python 3...
Verilog, Verilog HDL, RTL, Architecture, STA, Lint, CDC, Python 3, Windows...
Verilog, RTL, Architecture, STA, Lint, Python 3, Windows, PyCharm, Python, APIs...




Preferred Environment

Windows, PyCharm, Architecture

The most amazing...

...feat I've accomplished was taking ownership of the entire project delivery for a QSFP module development.

Work Experience

Staff Design Engineer

2022 - PRESENT
Imagination Technologies
  • Delivered an in-house media access control (MAC) intellectual property project, leading it from end to end, overseeing linting and clock-domain crossing (CDC) clean processes, and conducting self-unit testing to meet specified timing goals.
  • Acknowledged by the company's vice president for the work I've done and the impactful results achieved.
  • Used Jira for bug tracking, Python scripting for automation tasks, and SystemVerilog for verification purposes.
Technologies: RTL, Verilog, AIX, Architecture, PCIE, CXL, MacOS, STA, Lint, CDC, Python 3, Windows, PCI Express, Python

Senior Logic Design Engineer

2018 - 2022
  • Contributed to the development of register-transfer level (RTL) intellectual property targeting FPGA platforms and QSFP, PCIe, and I2C modules.
  • Took ownership of the entire project delivery, handling linting, clock-domain crossing (CDC) checks, and static timing analysis (STA). Used HSDS and Jira to track the project's progress.
  • Completed the tape-out process for two projects targeting the FPGA platform and QSFP module.
Technologies: Verilog, Verilog HDL, RTL, Architecture, STA, Lint, CDC, Python 3, Windows, PyCharm, PCI Express, Python

Hardware Design Engineer

2015 - 2018
  • Designed hardware solutions for SD-WAN technology, edge computing, and security protocols like MACsec/IPsec.
  • Used Scrubber, Jira, and HSDS for tracking bugs, and leveraged Webex and Teams to facilitate seamless collaboration and communication.
  • Developed an efficient hardware design specifically tailored for SD-WAN technology with MACsec IP integration.
Technologies: Verilog, RTL, Architecture, STA, Lint, Python 3, Windows, PyCharm, Python, APIs, Django

QSFP Module

A module within an FPGA platform specifically designed to connect with an external Ethernet module.

The QSFP controller within the QDFP module facilitates communication with the connected module and retrieves data. To handle data transfer, AXI Stream was used as the data lane protocol and AXI Slave Interfaces for register mapping. The I2C communication protocol was used for connecting with external modules.

In the design process, the Design Compiler tool was used to synthesize code, and the Altera Quartus software was utilized for validation on the FPGA platform. Finally, Spyglass was used for linting and CDC analysis.
2012 - 2014

Master of Technology Degree in Very Large Scale Integration (VLSI) Design

Vellore Institute of Technology - Chennai, India




MacOS, AIX, Windows


Python, Verilog, Verilog HDL, Python 3




STA, CDC, PCI Express, APIs, RTL, Architecture, PCIE, Artificial Intelligence (AI), Lint, CXL

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