Jay Yan, Developer in Milton Keynes, United Kingdom
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Jay Yan

Verified Expert  in Engineering

Software Developer

Location
Milton Keynes, United Kingdom
Toptal Member Since
May 2, 2022

Jay is an FPGA and ASIC design expert with extensive experience in real-time data processing, hardware accelerators, embedded system design, and edge computing. He is fluent with SystemVerilog and VHDL for traditional RTL design flow and C and C++ for high-level synthesis flow. He has experience in using UVM and formal methods for RTL design verification. Jay can also deliver software applications in bare metal, RTOS, and Linux environments for FPGA and ASIC integrations.

Portfolio

A Technology Company in the Automotive Industry
Intel Quartus Prime, Questa Sim, UVM, Jenkins, VHDL, SystemVerilog, Python, C...
Tech Startup
FPGA, Verilog, Verilog HDL, VHDL, Hardware Design, Hardware, C++, Xilinx Vivado...
NCR
Verilog HDL, Formal Methods, Image Processing, CMOS Image Sensors...

Experience

Availability

Part-time

Preferred Environment

Intel Quartus Prime, Xilinx Vivado, Questa Sim, Visual Studio Code (VS Code), Git, SymbiYosys, Jenkins

The most amazing...

...project I've contributed to is an ASIC-based video computation platform which is the core of next-generation augmented reality satnav.

Work Experience

FPGA/ASIC Design Engineer

2020 - PRESENT
A Technology Company in the Automotive Industry
  • Used Intel and Altera Arria 10 device as a prototype platform for ASIC tape-out validation.
  • Developed a UVM-based environment for end-to-end system verification and simulation.
  • Implemented display panel model in Intel and Altera Arria 10 FPGA for system validation.
  • Developed Jenkins server for FPGA/ASIC project continuous integration and continuous delivery. A Python script was written to build the Quartus project on the Jenkins server.
Technologies: Intel Quartus Prime, Questa Sim, UVM, Jenkins, VHDL, SystemVerilog, Python, C, FPGA, Embedded Systems

FPGA Developer

2022 - 2023
Tech Startup
  • Used a Xilinx Zynq Ultrascale+ device to build a video streaming platform to connect a wireless video source with an OLED display panel.
  • Integrated V-by-One IP into a video process pipeline to drive the OLED display panel.
  • Configured a Linux kernel to drive the Xilinx PCIe host IP and Intel PCIe WiFi device.
  • Used a Xilinx Zynq Ultrascale+ Video Codec Unit to receive an H.264/H.265 video stream and built a video processing pipeline in programmable logic.
Technologies: FPGA, Verilog, Verilog HDL, VHDL, Hardware Design, Hardware, C++, Xilinx Vivado, Hardware Video Codecs, PetaLinux, Linux Kernel, Embedded Systems, Embedded C

Senior Electronics Engineer

2018 - 2020
NCR
  • Implemented Nios processor with customized CMOS image sensor controller in FPGA. It was the foundation of the next-generation image sensor fusion platform.
  • Developed proprietary DRAM controller for image processing. It maximized the bandwidth of low-end SDRAM for image processing purposes.
  • Applied formal methods (SymbiYosys) on RTL design verification.
  • Developed an embedded C application for the Nios processor.
Technologies: Verilog HDL, Formal Methods, Image Processing, CMOS Image Sensors, DRAM Controller, UVM, Embedded Systems, Embedded C

Lead Electronic Hardware Engineer

2014 - 2018
General Electric
  • Implemented an Ethernet packet processing accelerator in FPGA using Xilinx Vivado HLS with C and C++-based high-level synthesis flow. Very low latency data processing has been achieved.
  • Built an FPGA verification environment by using SystemVerilog and UVM.
  • Implemented signal processing algorithms in FPGA, including IIR and FIR filter, interpolation, and DFT. Xilinx Vivado HLS (C and C++-based high-level synthesis flow) and VHDL were used.
  • Integrated FPGA with edge computing software, including writing applications to access FPGA private memory space or shared DDR memory and validate implemented functions in bare-metal and Linux environments.
  • Implemented an IO interface to connect Xilinx Zynq to the real world, including standard IO protocols such as Ethernet, EtherCAT, and AXI and customized protocols that use SerDes and transceivers.
Technologies: Xilinx Vivado, Embedded Linux, VHDL, High-level Synthesis (HLS), Embedded Systems

Electronics Design Engineer

2004 - 2013
Huawei Technologies Co.
  • Modeled and implemented program clock reference tracking method when MPEG-2 TS packets are streamed over an IP network. Basically, it's a feasible way for FPGA to track hundreds of TV programs' time references.
  • Implemented video processing algorithms in FPGA. Original algorithms were written in C and had to be manually redesigned and translated into Verilog.
  • Supported customers to solve issues and provided system solutions. For example, the IPTV head-end project includes 600 SD channels and 100 HD channels for Etisalat UAE.
Technologies: Altera Cyclone, Xilinx Spartan, Verilog, Digital TV, Digital Circuit Design, Embedded Systems

Propriety DRAM Controller for Low-cost Image Processing Platform

An FPGA-based DRAM controller that maximizes SDRAM bandwidth for image processing. The controller can be implemented in low-end FPGAs such as Intel and Altera MAX10. We verified the design by applying formal methods.

Ethernet Packet Processing Accelerator for Ultra Low Latency Application

An FPGA-based Ethernet packet processing accelerator for digital substation protection. It has ultra-low latency to meet grid protection safety standards. The accelerator was written in C and C++ and can be synthesized by Xilinx Vivado HLS and used in most Xilinx FPGAs and SoCs.

Image Sensor Bridge Interface (Patent)

https://patents.google.com/patent/US20220132075A1
An image sensor bridge interface is provided. The interface is situated between an image sensor and a processor. The interface comprises an integrated circuit. The integrated circuit comprises a Field-Programmable Gate Array (FPGA) decoupled from both image signals provided by the image sensor and a processor connected to the integrated circuit. The FPGA separates Ultraviolet (UV) and Infrared (IR) data values from image sensor-provided image data and embeds the UV and IR data values within the horizontal blanking, vertical blanking, and/or active video components of a video feed. The video feed is provided from the integrated circuit to the processor using a standard video interface, and the processor provides the video feed or provides UV images, IR images, and Red, Green, and Blue (RGB) images separated from the video feed to a computing core of a host device.
2013 - 2014

Master's Degree in System on Chip

University of Southampton - Southampton, United Kingdom

2000 - 2004

Bachelor's Degree in Electronic Engineering

Hefei University of Technology - Hefei, China

Tools

Jenkins, Git

Languages

SystemVerilog, Verilog HDL, VHDL, Python, C, Embedded C, Verilog, C++

Platforms

Visual Studio Code (VS Code), Embedded Linux

Frameworks

SymbiYosys

Other

Intel Quartus Prime, Xilinx Vivado, Digital IC Design, CMOS Image Sensors, DRAM Controller, High-level Synthesis (HLS), Altera Cyclone, FPGA, Xilinx Spartan, Embedded Systems, UVM, Questa Sim, Analog Circuit Design, Microcontrollers, Formal Methods, Image Processing, Digital TV, Digital Circuit Design, Hardware, Hardware Design, Hardware Video Codecs, PetaLinux, Linux Kernel

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